Frequently Asked Questions

How to erase flash on devices when JTAG/SWD interface accidentally disabled or PLL programmed wrongly by application program that is already in flash?

It is possible to disable the JTAG/SWD interface on the processors (primarily LPC1xxx/2xxx series) from software. It is also possible to program the PLL wrong so that the processor hangs. If this happens, it can be impossible to communicate with the processor via the JTAG/SWD interface. The reason for this is that the application program in flash starts executing immediately after reset. A JTAG/SWD pod normally takes some time to start connecting to the processor. During this initial connection phase, the application program inside the processor can disable the JTAG/SWD interface or hangs the PLL. The internal flash must be erased to solve this situation. Pull the ISP enable signal low when powering the board. This signal is:
- P0.14 for LPC21xx/22xx
- P2.10 for LPC17xx/23xx/24xx
- PIO0_1 for LPC11xx/13xx
Immediately connect the processor UART channel (some processors also allow ISP operation via USB or CAN) to the ISP program (for example FlashMagic). Erase flash from inside the ISP program. This procedure ensures that the application program in internal flash never executes on the processor after powerup. Also make sure to actually power cycle the processor before entering ISP mode. A warm reset does not always reset the PLL to a known state after reset. Therefore a cold reset is needed, i.e., cycle the power.

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